1. Technical Field
The present invention relates to a test apparatus and an electronic device and, more particularly, the present invention relates to a test apparatus testing a memory under test and an electronic device housing a test circuit.
2. Related Art
Conventionally, as a test of a memory under test such as a semiconductor memory, a test is known to judge pass/fail of each memory cell by writing a prescribed logic value to each memory cell of the memory under test, reading the written logic value, and comparing the written logic value to an expected value. Pass/fail information of the memory cell is stored in a fail memory of the test apparatus.
The fail memory includes a plurality of memory cells corresponding one-to-one with a plurality of memory cells of the memory under test and stores pass/fail information of each memory cell of the memory under test in the corresponding memory cell included therein (see, e.g., Patent Document 1 and Patent Document 2). In such a case, writing of the pass/fail information to the fail memory is executed through a read-modify-write operation.
Patent Document 1: Unexamined Japanese Patent Application Publication No. 2005-259265
Patent Document 2: Unexamined Japanese Patent Application Publication No. 2005-259266
In recent years, a significant increase in a capacity of semiconductor memories has been accompanied by an increase in testing time. Because of this, it is desirable to shorten the testing time. In conventional testing, however, even in a case where each memory cell is either pass or fail, pass/fail information in the test is written to the memory cell of the corresponding fail memory through a read-modify-write operation. Because of this, the writing of the pass/fail information to the fail memory is greatly increased relative to the increased capacity of the semiconductor memory.